; Para el siguiente programa se obtivieron los valores de los registros para TMR0H Y TMR0L
; de la siguiente forma:
;
; frecuencia = numero * 100 {siendo el numero la seleccion del usuario}
; periodo = frecuencia^(-1)
;
; para la salida se sabe que para un ciclo de trabajo del 50% se tiene que tener el pin RB0
; a un nivel alto durante un tiempo de (periodo/2) y a un nivel bajo durante un tiempo de (periodo/2)
; obteniendo asi la siguiente tabla:
;
; | numero | frecuencia | periodo/2 en us |
; 1 100 5000
; 2 200 2500
; 3 300 1667
; 4 400 1250
; 5 500 1000
; 6 600 833
; 7 700 714
; 8 800 625
; 9 900 556
; A 1000 500
;
; de esta forma definimos que cuando el timer0 se desborde realice la funcion de conmutar el pin RB0
; a los intervalos de tiempo obtenidos anteriormente.
;
; Debido a que el timer0 lo seleccionamos a 16 bits(con lo que tenemos 2^16 valores distintos), tenemos que
; modificar el valor del timer para que desvorde a la cantidad de pulsos obtenidos arriba por lo que aplicamos
; la siguiente formula:
;
; ValorRegistroTimer0 = (2^16)-(periodo/2 en us)
;
; De esta forma obtenemos la siguiente tabla:
;
; | periodo/2 | ValorRegistroTimer0 (en decimal) | ValorRegistroTimer0 (en hexadecimal) |
; 5000 60536 0XEC78
; 2500 63036 0XF63C
; 1667 63869 0XF97D
; 1250 64286 0XFB1E
; 1000 64536 0XFC18
; 833 64703 0XFCBF
; 714 64822 0XFD36
; 625 64911 0XFD8F
; 556 64980 0XFDD4
; 500 65036 0XFE0C
;
; Se selecciona el cristal interno a 4MHZ para obtener un tiempo de ciclo de 1us, de esta forma al multiplicar
; (periodo/2)*1us da como resultado el tiempo esperado.
LIST P=PIC18F4520 ; TIPOD DE MICRO
INCLUDE <p18f4520.inc> ;LIBRERIA DE REGISTROS
; CONFIG1H
CONFIG OSC = INTIO67 ; Oscillator Selection bits (Internal oscillator block, port function on RA6 and RA7)
CONFIG FCMEN = OFF ; Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
CONFIG IESO = OFF ; Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)
; CONFIG2L
CONFIG PWRT = OFF ; Power-up Timer Enable bit (PWRT disabled)
CONFIG BOREN = SBORDIS ; Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))
CONFIG BORV = 3 ; Brown Out Reset Voltage bits (Minimum setting)
; CONFIG2H
CONFIG WDT = OFF ; Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
CONFIG WDTPS = 32768 ; Watchdog Timer Postscale Select bits (1:32768)
; CONFIG3H
CONFIG CCP2MX = PORTC ; CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
CONFIG PBADEN = ON ; PORTB A/D Enable bit (PORTB<4:0> pins are configured as analog input channels on Reset)
CONFIG LPT1OSC = OFF ; Low-Power Timer1 Oscillator Enable bit (Timer1 configured for higher power operation)
CONFIG MCLRE = OFF ; MCLR Pin Enable bit (RE3 input pin enabled; MCLR disabled)
; CONFIG4L
CONFIG STVREN = ON ; Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
CONFIG LVP = OFF ; Single-Supply ICSP Enable bit (Single-Supply ICSP disabled)
CONFIG XINST = OFF ; Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))
; CONFIG5L
CONFIG CP0 = OFF ; Code Protection bit (Block 0 (000800-001FFFh) not code-protected)
CONFIG CP1 = OFF ; Code Protection bit (Block 1 (002000-003FFFh) not code-protected)
CONFIG CP2 = OFF ; Code Protection bit (Block 2 (004000-005FFFh) not code-protected)
CONFIG CP3 = OFF ; Code Protection bit (Block 3 (006000-007FFFh) not code-protected)
; CONFIG5H
CONFIG CPB = OFF ; Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)
CONFIG CPD = OFF ; Data EEPROM Code Protection bit (Data EEPROM not code-protected)
; CONFIG6L
CONFIG WRT0 = OFF ; Write Protection bit (Block 0 (000800-001FFFh) not write-protected)
CONFIG WRT1 = OFF ; Write Protection bit (Block 1 (002000-003FFFh) not write-protected)
CONFIG WRT2 = OFF ; Write Protection bit (Block 2 (004000-005FFFh) not write-protected)
CONFIG WRT3 = OFF ; Write Protection bit (Block 3 (006000-007FFFh) not write-protected)
; CONFIG6H
CONFIG WRTC = OFF ; Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
CONFIG WRTB = OFF ; Boot Block Write Protection bit (Boot block (000000-0007FFh) not write-protected)
CONFIG WRTD = OFF ; Data EEPROM Write Protection bit (Data EEPROM not write-protected)
; CONFIG7L
CONFIG EBTR0 = OFF ; Table Read Protection bit (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks)
CONFIG EBTR1 = OFF ; Table Read Protection bit (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks)
CONFIG EBTR2 = OFF ; Table Read Protection bit (Block 2 (004000-005FFFh) not protected from table reads executed in other blocks)
CONFIG EBTR3 = OFF ; Table Read Protection bit (Block 3 (006000-007FFFh) not protected from table reads executed in other blocks)
; CONFIG7H
CONFIG EBTRB = OFF ; Boot Block Table Read Protection bit (Boot block (000000-0007FFh) not protected from table reads executed in other blocks)
#define _file 1 ;DESTINO ARCHIVO EN LA MANIPULACION DE REGISTROS.
#define _wreg 0 ;DESTINO W EN LA MANIPULACION DE REGISTROS.
#defi
