PIPELINE

Mer som dette

MARS COLONY

Ved Borna Stojčić Mureta

RTI Framework

Ved Brooke Adams

LTRC Map 1

Ved LTRC 519

SIPSA 2017

Ved Jessica Hara

PIPELINE

STAGES

Write back

Memory Access

Execute

Decode

Fetch

CONFLICTS

Interrupt

Data Hazards

Timing Variations

DEFINATION

The process of storing and prioritizing computer instructions that the process that the processor executes.

TYPES

Instruction pipelining

Arithmetic Pipeline

MAIN AIM

To increase performance of processor by introducing faster technology.

To increase the overall instruction throughput.